1. Field of the Invention
The present invention relates to a clock forming method for a semiconductor integrated circuit and a program product for the method, and more particularly, to the method and the program product for the improved on-chip-variation resistance.
2. Background Art
It is difficult to supply a clock accurately and correctly to all sequential elements of a large scale semiconductor integrated circuit (LSI). In ordinary cases, a clock is supplied to different portions at different times. The difference between times at which a clock is supplied is called a clock skew. With the increase in packaging density and the increase in degree of integration of LSIs, a need has arisen to reduce clock skews of a clock applied to different portions. Clock skews are produced mainly at the design stage. Therefore, clock skew control with high accuracy is required when a clock is formed.
In Japanese Unexamined Patent Publication No. 8-129576, a layout method described below. First, the size, shape and other properties of blocks and inter-block wiring channels are accurately estimated and a block arrangement is determined. Arrangement and wiring in each block are thereafter performed to reduce the clock skew from an external clock terminal to a clock terminal in the block. Further, wiring layout is performed so that the clock skew from a clock generation source to the external clock terminal is within a predetermined range.
FIG. 5 is a diagram showing an example of synthesis of a clock tree by a conventional clock forming method. Four flip-flops (FF) are placed in each of regions G1 to G8 in a circuit region 1. The regions G1 to G4 and the regions G5 to G8 are separated from each other by a boundary 2. Further, the regions G1 and G2 and the regions G3 and G4 are separated by a boundary 3a and the regions G5 and G6 and the regions G7 and G8 are separated by a boundary 3b. 
A clock driver 4 is provided in each of the regions G1 to G8 and is connected to the FFs in the area. An upper-order clock driver 5 is provided between each of the adjacent pairs of the regions G1 and G2, G3 and G4, G5 and G6, and G7 and G8 to connect the clock drivers 4 in the adjacent pair of the regions. At each of the boundaries 3a and 3b, a further upper-order clock driver 6 is provided to connect the clock drivers 5. There are also provided data connection channels A1 to A4, B1 to B3, and C1 to C3 for data transfer between the regions.
Clock buffers (not shown) are connected to the clock drivers. Delay adjustment is performed so that the values of delays of clock signals to clock terminals of the FFs seen from the clock buffers are equal to each other. More specifically, arrangement and adjustment of clock buffers and insertion of a delay element to a faster path are performed. If a tool for performing such operates in an ideal manner, the delays of clock signals from a clock start point to all the FFs at terminal ends can be made equal to each other to reduce the clock skew to zero.
The above-described method is a clock forming method of reducing the clock skew to zero without considering on-chip variation. In actuality, however, on-chip variation exists. Therefore, if the data connection channels are not uniform, a difference occurs between an assumed delay value and the delay value on an actual device, so that the actual clock skew is not reduced to zero.
FIG. 6 shows the structure of a clock tree when data transfer is performed between the regions G2 and G5 (via the data connection channel A1) shown in FIG. 5. In this case, the clock signal passes through the clock drivers 4, 5, and 6. It is assumed here that the delay value with respect to one clock driver stage in a situation without consideration of on-chip variation is 1 ns, and that delay variation of ±10% due to on-chip variation occurs randomly. The delay value when on-chip variation is not considered is 3 ns. If on-chip variation of ±10% is considered, the delay value with respect to the data connection channel A1 is in the range from 2.7 to 3.3 ns and a skew of 600 ps (0.6 ns) at the maximum occurs.
FIG. 7 shows the structure of a clock tree when data transfer is performed between the regions G1 and G3 (via the data connection channel B1) shown in FIG. 5. In this case, the clock signal passes through the clock drivers 4 and 5. If the same assumption as that in the above is made, the delay value when on-chip variation is not considered is 2 ns. If on-chip variation of ±10% is considered, the delay value with respect to the data connection channel B1 is in the range from 1.8 to 2.2 ns and a skew of 400 ps (0.4 ns) at the maximum occurs. Similarly, when data transfer is performed via one of the data connection channels C1 to C3 shown in FIG. 5, the clock signal passes through the clock in one stage. Accordingly, the delay value of these data connection channels is in the range from 0.9 to 1.1 ns and a skew of 200 ps (0.2 ns) at the maximum occurs.
Any division of the regions G1 to G8 shown in FIG. 5 is not effective in preventing the occurrence of the above-described skew. Even in a situation where a large skew occurs when on-chip variation is considered, there is no problem in practice if data transfer is not performed between the corresponding regions. Conversely, if data transfer is performed between the regions between which a large skew can occur due to on-chip variation, there is a need to take measures to prevent the occurrence of a hold error and a setup error by considering on-chip variation.
In the above-described conventional clock forming method, a clock is formed without consideration of on-chip variation so that the clock skew is zero. There is, therefore, a problem that even if the clock skew reduced to zero, the clock skew increases on an actual device when on-chip variation is considered.